A LOW POWER BASED 8×8SRAM ARRAY USING MULTI THRESHOLD -CMOS TECHNIQUE AND VARIABLE THRESHOLD -CMOS TECHNIQUE
Keywords:
Low power, Static random-access memory, SRAM Array, Multi Threshold CMOS Technique (MTCMOS), Variable Threshold CMOS Technique (VTCMOS).Abstract
All modern high speed VLSI circuits need some kind of data storage. Static randomaccess memory (SRAM) is a commonly utilised memory in consumer electronics that serves tostore and retrieve huge amounts of data quickly. Therefore, a very power-efficient design is required. Low power approaches are necessary to obtain low power SRAM cells. The first step indesigning an 8×8 SRAM array
References
Robert Giterman, MaozVicentowski, Itamar Levi, YoavWeizman, OsnatKeren and Alexander Fish., “Leakage Power Attack-Resilient Symmetrical 8T SRAM Cell,” IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS”, no.5, May. 2018.
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Published
2024-12-20
How to Cite
RADHIKA.B.K. MADHAVI. (2024). A LOW POWER BASED 8×8SRAM ARRAY USING MULTI THRESHOLD -CMOS TECHNIQUE AND VARIABLE THRESHOLD -CMOS TECHNIQUE. Journal of Computational Analysis and Applications (JoCAAA), 33(08), 6132–6142. Retrieved from https://eudoxuspress.com/index.php/pub/article/view/3625
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