Verilog HDL-Based Design of a 16-Byte Asynchronous FIFO with Gray-Code Synchronization for Real-Time Systems
Keywords:
Asynchronous FIFO, Gray Code, Verilog HDL, FIFO Memory, Clock Domain Crossing (CDC), Metastability Reduction, Read/Write Pointer, Dual Clock FIFO, Digital Design, VLSI Design, FPGA Implementation, Real-Time Systems, Data Synchronization, High-Speed Data Transfer, Hardware Design, Memory Architecture, Low Latency, Embedded Systems, RTL Design, Flip-Flop SynchronizerAbstract
The proposed AGC-FIFO algorithm presents an efficientdesign for a 16-byte asynchronous FIFO memory usingGray code synchronization for real-time applications. Thesystem operates with independent read and write clock domains, ensuring reliable data transfer across asynchronousboundaries. Initially, binary read and write pointers aregenerated and converted into Gray code to minimize
References
[1] H. -J. Tseng et al., "28nm 0.3V 1W2R Sub-Threshold FIFO Memory for Multi-Sensor IoT Applications," in 2019 32nd IEEE International System-on-Chip Conference (SOCC), Singapore, 2019, pp. 248-253, doi: 10.1109/SOCC46988.2019.1570555748.
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Published
2025-10-15
How to Cite
Dr.P.Suneel Kumar,Dr.A.Nagarjuna Reddy,Dr Md Nazmoddin,Dr. P.Avinash. (2025). Verilog HDL-Based Design of a 16-Byte Asynchronous FIFO with Gray-Code Synchronization for Real-Time Systems. Journal of Computational Analysis and Applications (JoCAAA), 34(10), 539–548. Retrieved from https://eudoxuspress.com/index.php/pub/article/view/5894
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