DYNAPACE-AI: A Deadline- and Thermal-Aware Multi-Voltage VLSI Architecture  for Energy-Scalable AI-Enabled Embedded Systems

Ratan Babu Telusoori, Dr, Vikas Jaiman

DYNAPACE-AI: A Deadline- and Thermal-Aware Multi-Voltage VLSI Architecture for Energy-Scalable AI-Enabled Embedded Systems

Authors

Ratan Babu Telusoori, Dr, Vikas Jaiman

Keywords:

embedded AI, VLSI accelerator, DVFS, multi-voltage domain, power gating, thermal aware computing, edge inference, energy efficiency, neural-network accelerator.

Abstract

Artificial-intelligence-enabled embedded systems must meet inference deadlines while operating fromrestricted battery, power-delivery, and thermal budgets. Conventional neural-network accelerators arecommonly designed around a fixed worst-case supply voltage and frequency, causing unnecessary dynamic power and leakage whenever the instantaneous workload contains computational slac

References

[1] M. Horowitz, “1.1 Computing’s Energy Problem (and What We Can Do About It),” 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 10–14, 2014.

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Published

2024-08-20

How to Cite

Ratan Babu Telusoori, Dr, Vikas Jaiman. (2024). DYNAPACE-AI: A Deadline- and Thermal-Aware Multi-Voltage VLSI Architecture for Energy-Scalable AI-Enabled Embedded Systems. Journal of Computational Analysis and Applications (JoCAAA), 33(08), 7724–7740. Retrieved from https://eudoxuspress.com/index.php/pub/article/view/5823