Design and Implementation of a Low-Power FPGA-Based Architecture for Deep Neural Network Acceleration in Edge Computing Systems
Keywords:
Edge Computing, FPGA Acceleration, Deep Neural Networks, Edge Intelligence, INT8 Quantization, Energy Efficiency, Hardware Optimization.Abstract
The increasing adoption of edge computing has created a growing demand for efficient deploymentof deep neural networks (DNNs) on resource-constrained devices. While cloud-based inferenceoffers high computational power, it often suffers from latency, bandwidth limitations, and privacy concerns, making it unsuitable for many real-time edge applications. To address these challenges,this paper proposes a low-power FPGA-based architecture for accelerating
References
1. Chen, Y. H., Emer, J., & Sze, V. (2016). Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks. In Proceedings of the 43rd Annual International Symposium on Computer Architecture (ISCA) (pp. 367–379). IEEE. https://doi.org/10.1109/ISCA.2016.40
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Published
2026-07-16
How to Cite
Dr Yaser Madani ,Javad Shahrabi Farahani. (2026). Design and Implementation of a Low-Power FPGA-Based Architecture for Deep Neural Network Acceleration in Edge Computing Systems . Journal of Computational Analysis and Applications (JoCAAA), 35(7), 89–106. Retrieved from https://eudoxuspress.com/index.php/pub/article/view/5698
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