Clock Domain Crossing Effects and Verification Challenges in Modern VLSI Systems
Keywords:
Clock Domain Crossing, Metastability, Synchronization, VLSI Verification, Multi-Clock ArchitectureAbstract
Clock Domain Crossing (CDC) is the most important issue in current VLSI systems design becausesemiconductor architectures are using multiple autonomous clock domains more often to design the bestperformance and power efficiency. Signal communication between asynchronous clock domains bringsabout metastability, which is an inherent physical phenomenon that cannot be precisely modeledusing standard RTL or gate-level simulation tools.
References
Clifford E. Cummings, "Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog," Sunburst Design. [Online]. Available: http://staff.ustc.edu.cn/~wyu0725/FPGA/snug_collection/1Sunburst%20Design/Clock%20Domain%20Cr ossing%20(CDC)%20Design%20&%20Verification%20Techniques%20Using%20SystemVerilog.pdf
