Analysis of Clock Trees for Optimization through Multi-Point Clock Tree  Synthesis in Advanced Nodes

Dr. Sandeep Santosh

Analysis of Clock Trees for Optimization through Multi-Point Clock Tree Synthesis in Advanced Nodes

Authors

Dr. Sandeep Santosh

Keywords:

Clock Tree Synthesis (CTS), Multi-CTS, Skew Optimization, Low Power Design, VLSI Physical Design, Ad- vanced Nodes, Machine Learning.

Abstract

Clock Tree Synthesis (CTS) is a critical stage in VLSI physical design, directly impactingtiming closure, power consumption, and signal integrity. Traditional single-root CTSmethodologies struggle with scalability in modern System-on- Chips (SoCs) at advanced process nodes due

References

J. Smith, A. Lee, and R. Gupta, ”Multi-Point Clock Tree Synthesis for Low-Skew Optimization in VLSI,” IEEE Trans. VLSI Syst., vol.33, no.1, 2025

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Published

2024-08-20

How to Cite

Dr. Sandeep Santosh. (2024). Analysis of Clock Trees for Optimization through Multi-Point Clock Tree Synthesis in Advanced Nodes . Journal of Computational Analysis and Applications (JoCAAA), 33(08), 6813–6825. Retrieved from https://eudoxuspress.com/index.php/pub/article/view/4013