AI-Engine-Based Acceleration for High-Performance Programmable  System-on-Chip Designs

Bhanu Prakash Reddy Rella, Ashmita Chakraborty, Sagar Bharat ShahHemanta Ghosh, Shubham Gautam, Bhavesh Arjan Dhirwani,Sree Pradeep Kumar Relangi, Nilesh Mutyam

AI-Engine-Based Acceleration for High-Performance Programmable System-on-Chip Designs

Authors

Bhanu Prakash Reddy Rella, Ashmita Chakraborty, Sagar Bharat ShahHemanta Ghosh, Shubham Gautam, Bhavesh Arjan Dhirwani,Sree Pradeep Kumar Relangi, Nilesh Mutyam

Keywords:

Abstract

This research paper, titled "Optimizing the Performance of Programmable System-on-Chip Architectures UsingAI Engines", presents an in-depth study of heterogeneous computing platforms, which are increasingly central tomodern high-performance computing (HPC) applications. With the growing reliance on GPUs, FPGAs, and datacenter accelerators, significant progress has been made in reducing computational latency and enhancingthroughput. Architectures that integrate heterogeneous componentssuch as CPU-FPGA or CPU-GPU

References

Y. Shen et al., “Towards a Uniform Accelerator Interface for Deep Neural Networks on FPGAs,” Proc. ACM/SIGDA FPGA, 2017.

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Published

2024-01-22

How to Cite

Bhanu Prakash Reddy Rella, Ashmita Chakraborty, Sagar Bharat ShahHemanta Ghosh, Shubham Gautam, Bhavesh Arjan Dhirwani,Sree Pradeep Kumar Relangi, Nilesh Mutyam. (2024). AI-Engine-Based Acceleration for High-Performance Programmable System-on-Chip Designs . Journal of Computational Analysis and Applications (JoCAAA), 32(1), 894–906. Retrieved from https://eudoxuspress.com/index.php/pub/article/view/3351