FULL CUSTOM DESIGN AND IMPLEMENTATION OF HIGH PERFORMANCE ADDER
Keywords:
10 transistor adder, full custom, optimization.Abstract
In this paper we present the design of a 10 transistor (10T) full adder optimized for low powerand low area, suitable for portable and energy efficient VLSI applications. The design utilizestwo XOR gates and one multiplexer, to minimize transistor count while achieving correct
References
Ajit Anaswar, P.V. Arathi, Kiran Haridas, Niraj Mohan Nambiar, and S. Devi, “FPGA based performance comparison of different basic adder topologies with parallel processing adder,” in 2019 3rd International Conference on Electronics, Communication and Aerospace Technology (ICECA). IEEE, 2019.
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Published
2022-02-21
How to Cite
A. Lakshmi,Dr.P.Chandrasekhar ReddyEsther Rani Thuraka3. (2022). FULL CUSTOM DESIGN AND IMPLEMENTATION OF HIGH PERFORMANCE ADDER . Journal of Computational Analysis and Applications (JoCAAA), 30(2), 662–676. Retrieved from https://eudoxuspress.com/index.php/pub/article/view/3215
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