DESIGN OF A MEALY FSM FOR COMPARING TWO 4-BIT UNSIGNED  NUMBERS WITH CHECK BIT INPUT

Mr.K.Ch.MALLA REDDY  , Mr.A.PRASAD , PIDATALA HIMAJA , THIMMISETTI HEMALATHA , SANDIREDDY LAKSHMI DEVI, VENNA MOUNIKA

DESIGN OF A MEALY FSM FOR COMPARING TWO 4-BIT UNSIGNED NUMBERS WITH CHECK BIT INPUT

Authors

Mr.K.Ch.MALLA REDDY , Mr.A.PRASAD , PIDATALA HIMAJA , THIMMISETTI HEMALATHA , SANDIREDDY LAKSHMI DEVI, VENNA MOUNIKA

Keywords:

Abstract

This paper presents the design of a Mealy finite state machine (FSM) for comparing two 4-bit unsignednumbers. The numbers are received serially, with the least significant bit (LSB) arriving first. Additionally, a check-bitinput (C) is used to indicate when the last bit of the 4-bit numbers has been received

References

Digital Design" by Morris Mano and Michael Ciletti*

"Logic and Computer Design Fundamentals" by Charles H. Roth Jr. and Larry L. Kinney*

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Published

2024-12-11

How to Cite

Mr.K.Ch.MALLA REDDY , Mr.A.PRASAD , PIDATALA HIMAJA , THIMMISETTI HEMALATHA , SANDIREDDY LAKSHMI DEVI, VENNA MOUNIKA. (2024). DESIGN OF A MEALY FSM FOR COMPARING TWO 4-BIT UNSIGNED NUMBERS WITH CHECK BIT INPUT . Journal of Computational Analysis and Applications (JoCAAA), 33(08), 3875–3880. Retrieved from https://eudoxuspress.com/index.php/pub/article/view/2635