DESIGN AND IMPLEMENTATION OF ASYNCHRONOUS FIFO WITH  DUAL CLOCK DOMAIN IN VERILOG

Mr.B.AJANTHA REDDY , Dr.A.RANGANAYAKULU , ATCHUTA RAKESH, DUGGI RAMI REDDY, SREERAMULA SURESH, CHALLA UDAY KIRAN

DESIGN AND IMPLEMENTATION OF ASYNCHRONOUS FIFO WITH DUAL CLOCK DOMAIN IN VERILOG

Authors

Mr.B.AJANTHA REDDY , Dr.A.RANGANAYAKULU , ATCHUTA RAKESH, DUGGI RAMI REDDY, SREERAMULA SURESH, CHALLA UDAY KIRAN

Keywords:

Abstract

This paper presents the design and implementation of an Asynchronous FIFO (First-In-FirstOut) buffer in Verilog, where the write and read operations are controlled by two independent clockdomains. The FIFO buffer accepts 8-bit data inputs and provides 8-bit data outputs. It includes variousfeatures such as write enable, read enable

References

Digital Design and Computer Architecture by David Money Harris and Sarah L. Harris This book covers various aspects of digital system design, including the concept of FIFOs and their applications in systems like SPI. It is a comprehensive resource for understanding how FIFOs work in different digital communication protocols. Link: Digital Design and Computer Architecture

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Published

2024-12-17

How to Cite

Mr.B.AJANTHA REDDY , Dr.A.RANGANAYAKULU , ATCHUTA RAKESH, DUGGI RAMI REDDY, SREERAMULA SURESH, CHALLA UDAY KIRAN. (2024). DESIGN AND IMPLEMENTATION OF ASYNCHRONOUS FIFO WITH DUAL CLOCK DOMAIN IN VERILOG. Journal of Computational Analysis and Applications (JoCAAA), 33(08), 3828–3834. Retrieved from https://eudoxuspress.com/index.php/pub/article/view/2628