DESIGN OF A MEALY FSM FOR SERIAL DATA RECEPTION WITH   EVEN PARITY CHECK ON 8-BIT BLOCKS

Mr.A.PRASAD  , Mr.N.B.JILANI  , KOTLA GURAVA REDDY , SHAIK KHASIM SHARIF , A VENNA HARIKRISHNA REDDY, DANDA NAGENDRA REDDY

DESIGN OF A MEALY FSM FOR SERIAL DATA RECEPTION WITH EVEN PARITY CHECK ON 8-BIT BLOCKS

Authors

Mr.A.PRASAD , Mr.N.B.JILANI , KOTLA GURAVA REDDY , SHAIK KHASIM SHARIF , A VENNA HARIKRISHNA REDDY, DANDA NAGENDRA REDDY

Abstract

In this work, we design a Mealy finite state machine (FSM) for synchronously receiving serial 1bit data and performing a parity check on every 8-bit block. The FSM is triggered by a start signal, withdata reception continuing until the start signal is deasserted. A timer signal, T, marks the end of every 8-bitreception,

References

Harel, D. (1987). "Statecharts: A Visual Formalism for Complex Systems." Science of Computer Programming, 8(3), 231-274. This paper introduces statecharts, an extension of finite state machines (FSMs), which are relevant for designing complex state machines such asthose used for serial data reception.

Hopcroft, J. E., & Ullman, J. D. (1979). Introduction to Automata Theory, Languages, and Computation. AddisonWesley.

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Published

2024-12-11

How to Cite

Mr.A.PRASAD , Mr.N.B.JILANI , KOTLA GURAVA REDDY , SHAIK KHASIM SHARIF , A VENNA HARIKRISHNA REDDY, DANDA NAGENDRA REDDY. (2024). DESIGN OF A MEALY FSM FOR SERIAL DATA RECEPTION WITH EVEN PARITY CHECK ON 8-BIT BLOCKS. Journal of Computational Analysis and Applications (JoCAAA), 33(08), 3821–3827. Retrieved from https://eudoxuspress.com/index.php/pub/article/view/2626