DESIGN AND IMPLEMENTATION OF SELECTABLE COUNTER WITH MUTLIPLE COUNTING MODES IN VERILOG

Abstract

This paper presents the design and implementation of a selectable counter in Verilog,capable of operating in four different counting modes: Up Counter, Down Counter, Decade Counter,and Johnson Counter. The counter is controlled by a select signal (sel), which determines thecounting mode, and an enable signal (en) that controls the counter operation. The counter alsoincorporates a reset signal (rst) to reset its state to zero. The paper provides an e