DESIGN AND IMPLEMENTATION OF A MEALY FSM FOR DETECTING INPUT SEQUENCES AND GENERATING OUTPUTS
Keywords:
.Abstract
This paper describes the design and implementation of a Mealy finite state machine (FSM) thatgenerates two outputs, Z1 and Z2, based on the input sequence din. The machine should assert Z1=1 whenthe sequence 101 is observed, provided that the sequence 011 has never been detected. If the sequence 011is observed, the machine asserts Z2=1, and thereafter, Z1=1 can no longer be asserted. The design uses aMealy FSM approach, where the outputs are based on both the current state and the input. Verilog code forthe FSM is provided, along with a testbench to validate the functionality under various input conditions
References
Karp, R. M., & Rabin, M. O. (1959). Efficient Algorithms for Finding Maximum Matching in Graphs. Proceedings of the American Mathematical Society, 10(2), 265-271. This early work on automata and pattern recognition laid the groundwork for FSMs, especially in the context of sequence detection and graph-based problems.
Knuth, D. E., Morris, J. H., & Pratt, V. R. (1977). Fast Pattern Matching in Strings. SIAM Journal on Computing, 6(2), 323-350.
