DESIGN OF A CLOCK GENERATOR WITH 70% DUTY CYCLE FOR TIMING APPLICATIONS
Keywords:
.Abstract
This paper presents the design of a clock generator module in Verilog that produces a clock signalwith a 70% duty cycle. The system utilizes an input clock signal, which is divided using a counter, and theoutput clock toggles between high and low states based on pre-defined durations that result in a 70% hightime and 30% low time. The generated clock signal is useful in applications
References
Basker, P., & Kapoor, S. (2014). Design of a duty cycle generator using a counter. International Journal of Engineering and Technology, 6(1), 28-32. This paper discusses the design of a duty cycle generator using counters, which can be adjusted for different duty cycles, including 70%. It covers the logic and implementation of such systems.
Karthikeyan, S., & Srinivasan, S. (2013). A Duty Cycle Modulator for Digital Circuits. Proceedings of the International Conference on Communication Systems and Networks, 1-4.
