OPTIMIZING MULTIPLIER: A GLOBAL APPROACH FOR FPGA DESIGN
Keywords:
FPGA, multiplier optimization, digital signal processing, machine learning, power efficiencyAbstract
Field-Programmable Gate Arrays(FPGAs) have become integral in highperformance computing applications,particularly in digital signal processing(DSP) and machine learning tasks,where efficient multiplication is crucial.Traditional multiplier designs oftenface challenges
References
Parhami, B. (2010). Computer Arithmetic: Algorithms and Hardware Designs. Oxford University Press.
Chandrakasan, A., Brodersen, R. (1995). Low Power Digital CMOS Design. Kluwer Academic Publishers.
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Published
2024-04-16
How to Cite
Dr.SIVANAGI REDDY KALLI, ARAKALA SRIDEVI, ANUMALLA SRISINDHU, HANUMANDLA HARSHINI. (2024). OPTIMIZING MULTIPLIER: A GLOBAL APPROACH FOR FPGA DESIGN. Journal of Computational Analysis and Applications (JoCAAA), 33(4), 800–808. Retrieved from https://eudoxuspress.com/index.php/pub/article/view/2501
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