OPTIMIZED 64-BIT RADIX-16 BOOTH MULTIPLIER WITH ENHANCED PARTIAL PRODUCT REDUCTION FOR HIGH PERFORMANCE COMPUTING
Keywords:
Modified Booth Encoding, Radix-16, Pipeline, Multiplier, Enhanced, Carry Select Adder, Binary Excess Converter.Abstract
The Redundant Binary Partial Product Generator technique optimizes radix-16 Modified Booth Encoded multipliers by reducing the maximum height of the partial product array by one row without increasing the delay of the partial product creation block. This paper presents an improved binary radix-16 Booth recoded multiplier, minimizing the maximum height of partial product columns to [n/4] for 64-bit unsigned operands, compared to the conventional [(n+1)/4], achieving a one-unit reduction. This optimization enhances arithmetic multipliers, thereby improving the performance of ALUs and processors.
References
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F. Lamberti et al., “Reducing the computation time in (short bit-width) twos complement multipliers,” IEEE Trans. Comput., vol. 60, no. 2, pp. 148–156, Feb. 2011.
