High-Performance Vedic Multiplier with Modified HSCG-SCG Adder for Low-Power and High-Speed Arithmetic Processing
Keywords:
Adders, HSCG-SCG Adder, Multipliers, Vedic Multipliers, Verilog HDL, High-Speed Multiplication, Power Efficiency, Digital Signal Processing, Vivado.Abstract
Inspired by the concepts of ancient Vedic mathematics, the Modified Vedic Multiplier is a multiplication algorithm that uses a special method that combines crosswise and vertical computations. This study presents the Modified HSCG-SCG Adder, an enhanced variant of
conventional binary adders that uses a carry tree to calculate the final result and a decoder to produce partial products.
References
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