Design of Non Strobe Regenerative Sense Amplifiers for Low Power Application using at 45nm CMOS Technology

Abstract

In this paper introduces a novel sense amplifier to meet the demand of memory in the in a memory cell. To overcome the latency of sensing techniques in memory systems, a new sense amplifier (SA) is required for low power applications. SRAM outperforms all other types of memory, including volatile memory. The sensing latency is analyzed with C bit line and power delivery variations in mind. On the basis of area, power, and delay, the design of a sense amplifier was evaluated. In this paper a high-density SRAMs employ aggressively small bit-cells that are prone to extreme fluctuation, resulting in poorer read SNM and read-current. Furthermore, uncertainty in strobe timing and sense-amplifier offset limit array performance. This paper a non strobe regenerative sense-amplifier that addresses all of these performance issues: Simple offset compensation, in particular, reduces variation susceptibility while putting minimum load on high-speed nodes. Influence, and later, ultimate execution of recollection, rises. The designed is implemented in 45nm CMOS technology using Cadence virtuso EDA tools.