[1]
Dr.P.Suneel Kumar,Dr.A.Nagarjuna Reddy,Dr Md Nazmoddin,Dr. P.Avinash, “Verilog HDL-Based Design of a 16-Byte Asynchronous FIFO with Gray-Code Synchronization for Real-Time Systems”, Journal of Computational Analysis and Applications (JoCAAA), vol. 34, no. 10, pp. 539–548, Oct. 2025.