DR.P.SUNEEL KUMAR,DR.A.NAGARJUNA REDDY,DR MD NAZMODDIN,DR. P.AVINASH. Verilog HDL-Based Design of a 16-Byte Asynchronous FIFO with Gray-Code Synchronization for Real-Time Systems. Journal of Computational Analysis and Applications (JoCAAA), [S. l.], v. 34, n. 10, p. 539–548, 2025. Disponível em: https://eudoxuspress.com/index.php/pub/article/view/5894. Acesso em: 16 oct. 2026.