KAILASH SINHA, P. VENKATESH, SK AHMED PASHA. OPTIMIZED 64-BIT RADIX-16 BOOTH MULTIPLIER WITH ENHANCED PARTIAL PRODUCT REDUCTION FOR HIGH PERFORMANCE COMPUTING. Journal of Computational Analysis and Applications (JoCAAA), [S. l.], v. 32, n. 2, p. 77–84, 2024. Disponível em: https://eudoxuspress.com/index.php/pub/article/view/2062. Acesso em: 3 apr. 2025.