DESIGN OF A MEALY FSM FOR SERIAL DATA RECEPTION WITH EVEN PARITY CHECK ON 8-BIT BLOCKS - Mr.A.PRASAD , Mr.N.B.JILANI , KOTLA GURAVA REDDY , SHAIK KHASIM SHARIF , A VENNA HARIKRISHNA REDDY, DANDA NAGENDRA REDDY (Journal of Computational Analysis and Applications (JoCAAA), 2024)
In this work, we design a Mealy finite state machine (FSM) for synchronously receiving serial 1bit data and performing a parity check on every 8-bit block. The FSM is triggered by a start signal, withdata reception continuing until the start signal is deasserted. A timer signal, T, marks the end of every 8-bitreception,