DESIGN AND PERFORMANCE ANALYSIS OF VERTICAL  NANOWIRE TUNNEL FET FOR LOW POWER APPLICATIONS

Km Anjana Bhardwaj ,Dr Pradeep Kumar,Dr M Senthil Kumar

DESIGN AND PERFORMANCE ANALYSIS OF VERTICAL NANOWIRE TUNNEL FET FOR LOW POWER APPLICATIONS

Authors

Km Anjana Bhardwaj ,Dr Pradeep Kumar,Dr M Senthil Kumar

Keywords:

Tunnel FET, Vertical Nanowire, Low Power, TCAD Simulation, Subthreshold Swing, Band-to-Band Tunneling, Gate-All-Around

Abstract

The continuous scaling of CMOS technology has significantly improved device density andcomputational performance over the past decades. However, as device dimensions approach the nanometer regime, conventional MOSFET-based technologies

References

Borrowman, C., Howell, R., Mohata, D., Datta, S., Sampson, M. and Gupta, S. (2024) 'Application-specific TFET circuit design for ultra-low power systems', IEEE Transactions on Electron Devices, 71(2), pp. 445-458

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Published

2024-05-04

How to Cite

Km Anjana Bhardwaj ,Dr Pradeep Kumar,Dr M Senthil Kumar. (2024). DESIGN AND PERFORMANCE ANALYSIS OF VERTICAL NANOWIRE TUNNEL FET FOR LOW POWER APPLICATIONS. Journal of Computational Analysis and Applications (JoCAAA), 33(05), 3559–3574. Retrieved from https://eudoxuspress.com/index.php/pub/article/view/4947