SCALABLE VLSI ARCHITECTURE FOR HIGH-PERFORMANCE INTEGER TRANSFORM IN UHD HEVC VIDEO PROCESSING
Keywords:
Bit-plane matrix, HEVC, Integer Transform, Ultra High Definition, VLSI Architecture, DCT, Video Coding.Abstract
This research presents a versatile VLSI architecture for computing the N-point Discrete Cosine Transform DCT), a critical component in High-Efficiency Video Coding (HEVC). The HEVC standard supports multiple block sizes for DCT computation, ranging from 4 × 4 to 32 × 32, necessitating a flexible and efficient hardware design
References
N. Ahmed, T. Natarajan, and K. R. Rao, “On image processing and a discrete cosine transform,” IEEE Trans. Comput., vol. C-23, no. 1, pp. 90–93, Jan. 1974.
G. K. Wallace, “JPEG still image data compression standard,” Commun. ACM, vol. 34, no. 4, pp. 30–44, Apr. 1991.
Downloads
Published
2024-02-03
How to Cite
Sk Ahmed Pasha, D. Sumalatha, B. Vara Lakshmi. (2024). SCALABLE VLSI ARCHITECTURE FOR HIGH-PERFORMANCE INTEGER TRANSFORM IN UHD HEVC VIDEO PROCESSING. Journal of Computational Analysis and Applications (JoCAAA), 32(2), 69–76. Retrieved from https://eudoxuspress.com/index.php/pub/article/view/2061
Issue
Section
Articles
