High-Speed and Power-Efficient 2-Bit Binary Magnitude Comparator Design Using Pass Transistor Logic
Keywords:
Multiplexer, Magnitude Comparator, CMOS, Pass Transistor Logic, Tanner Eda, Power Efficiency, Speed Improvement.Abstract
In this study, a 2-bit binary Magnitude Comparator (MC) is designed using Pass Transistor Logic (PTL) and Conventional CMOS (CCMOS) logic. To evaluate its performance, the suggested MC design is put through simulation and contrasted with five different MC systems that are currently in use. The findings show that there are notable gains in speed and power efficiency with the suggested 2-bit MC configuration
References
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