Radiation-Resilient Memory: A 2D Code-Based Error Correction Technique for Mitigating Multiple Cell Upsets in Space Applications
Keywords:
On-Chip Memory Errors, Multiple Cell Upsets (MCUs), Radiation-Induced Errors, Error Correction Code (ECC), 2D Code-Based Correction, Divide-Symbol Methodology,Abstract
The essential problem of bit errors in on-chip memory within a die caused by a variety of external variables, including cosmic radiation, alpha and neutron particles, and severe temperatures in space, is discussed in this study. As technology advances, these errors might cause data corruption. The study presents a novel error correcting method based on a 2-dimensional code that use a divide-symbol
methodology to reduce these errors.
References
R. C. Baumann (2005), “Soft errors in advanced computer systems,” IEEE Des. Test. Comput., vol. 22, no. 3, pp. 258-266.
C. L. Chen and M. Y. Hsiao (1984), “Error-correcting codes for semiconductor memory applications: A state-of-the-art review,” IBM J. Res. Develop., vol.28, no. 2, pp. 124-134.
E. Ibe, S. Chung, S. Wen, H. Yamaguchi, Y. Yahagi, H. Kameyama, S. Yamamoto and T.Akioka (2006), “Spreading diversity in multi-cell neutron-induced upsets with device scaling,” in Proc. IEEE Custom Integrated Circuit Conf., pp. 437-444.
